CPU Abbreviation Meaning
The central processing unit (abbreviation commonly used: CPU), or central processor is a type of processor digital general purpose which is characterized by overseeing all of the features the computer based on the digital von Neumann architecture or on Harvard architecture.
It is the unit central processing because it centrally coordinates all other processing units present in the hardware architecture of the computer processing of the various peripheralsor internal electronic cards ( sound card , video card , network card) (eg. Co-processor andprocessor digital signal ).
The CPU task is to perform the reconstructions of a program present in main memory or primary (RAM) after it is taken from the secondary memory or mass, from the ROM, or other devices. During program execution, the CPU reads or writes data in main memory. Dell results execution depends on the data on which it operates and the internal state in which the CPU itself is located, and can keep track of instructions executed and the read data.
In current systems with multiple processing units, both to perform the instruction to perform specific autonomous functions, the “central” term has lost its meaning. There is no longer a central body that manages the system. The term CPU is therefore replaced by “Processor” (processor). For example there is the term “microprocessor” (and not microCPU), “multiprocessor” and “multicore” (and not multiCPU) that are antithetical to the concept of “central processor”. The term CPU is now obsolete and no longer used (or rarely used only for historical legacy).
A generic CPU contains:
- a control unit (also known by the acronym “CU” according to AbbreviationFinder.org) that reads instructions from memory, if necessary also reads the data for the instruction read, executes the statement, and stores the result if there is, by writing it in the memory or in a CPU register.
- an arithmetic and logic unit (also known by the acronym “ALU”) that deals with performing logical and arithmetic operations;
- of registers, special internal memory to the CPU locations, very fast, that you can more quickly access that memory: the total value of all CPU registers is the state in which it is currently located. Two registers are always present:
- IP register (Instruction Pointer) or PC (Program Counter), which contains the address in memory of the next instruction to be executed;
- the register of flag: this register does not contain conventional numerical values, but rather a set of bits, said just flag, which indicate particular states of the CPU and some information about the result of the last operation performed. The most important flags are:
- Status flags:
- Overflow: indicates if the previous operation result was too large for the result field: 0 absence of overflow, 1 overflow
- Zero: 1 if the last operation was a result zero, otherwise it is 0.
- Carry: (Fill) is 1 if the last operation has exceeded the capacity of the register that contains the result, otherwise it is 0 (example: in an 8-bit register, which can only represent numbers from 0 to 255, the sum 178+ 250 would result in 172, that is, 428-256, and the carry would be placed in 1 together with the overflow flag). In subtraction operations, obtained as the sum of the complement, instead has exactly the opposite meaning.
- Sign indicates the sign of the previous operation result: 0 positive, one negative. In fact there is no specific flag sign, but this is directly derived from the flag zero and carry. In the subtraction flag with zero = 0 = 1 and carry it has a positive sign, with carry = 0 negative.
- control flags:
- Interrupt: If this flag is assigned a value of 1, the CPU stops responding to external requests for service of devices (the IRQ line signals) until it is restored to the value 0, or until it receives a reset signal from the outside.
- Status flags:
A generic CPU must execute its tasks by synchronizing with the rest of the system: therefore is equipped, in addition to the above items, also of one or more internal buses that deal connect registers, ALU, memory and control units: also to CPU internal control unit includes a number of external electrical signals that deal to keep the CPU to the rest of the current state of the system and acting on it. The type and number of managed external signals may vary, but some, such as RESET, the lines IRQ and CLOCK are always present.
As regards the registers, the CPU can manage them in several ways: the most common are registers Names (CPU Classic CISC), register file (RISC) and the stack of registers ( transputer and the like).
- Stack of logs: the logs are arranged in a stack structure (stack); This architecture has the advantage of not having to specify on which internal register to operate (is always the top of the stack) getting shorter and more simple instructions to be decoded. The downside is that if you need a certain “buried” at the bottom of the stack, its recovery is a very slow.
- Names registers: each tab is individually identified and instructions which use registers specify from time to time which register should be used. Often some registers are dedicated to particular purposes (index registers, accumulators, segment registers etc.) By imposing the non-orthogonality of the instruction set (see below). The vast majority of generic CPU of the 70’s and 80’s of this type.
- Register file: The registers are organized as an internal memory of the CPU and indexed: the CPU “allocates” a number of registers for each process and/or subroutines running, eliminating the need to access the RAM to save the call stack the functions and task switching data in multitasking systems.
A CPU is a synchronous digital circuit: that is to say that its state changes every time it receives a pulse from a clock signal of said clock, which consequently determines the operating speed, said clock speed: therefore the execution time of an instruction is measured in clock cycles, that is, in how many clock pulses are necessary because the CPU to complete. In fact, an important and delicate part of each CPU is the distribution system that brings the clock signal to the various units and sub-units of which it is composed, to ensure that they are always in sync: the system branches into a structure to tree with dividers and repeaters that reaches everywhere in the CPU.
In most modern processors (Pentium , Athlon , PowerPC), this “of” electronic gear chain is able to employ about 30% of all available transistors. The speed of this distribution determines in a direct way the maximum operating frequency of a CPU: CPU can be no faster than its critical path, i.e the time it takes the clock to travel the longest stretch around the clock distribution tree. For example, if the clock signal of a given CPU employs a nanosecond to cross all the chip and get up to the last sub-unit, this CPU can operate at not more than 1 GHz, because otherwise its internal components would lose synchronization, with unpredictable results (to have a margin of safety, the practical limit will be well indeed less than 1 GHz).
Typically the CPU is the Interpreter of machine language. Like all performers, it is based on the following cycle:
- Education acquisition (Instruction Fetch): The processor fetches the instruction from memory, in the address (typicallylogic ) specified by a register “special” ( “special” opposite of “generic”), the PC
- Decoding (Operand Assembly): once theword was taken, is determined which operation is to be performed and how to get the operands, according to a function whose domain consists of the operating codes (typically the high bits of the word ) and the co-domain consists of the songs of the microprogram to be executed
- Execution (Execute): the desired computation is performed. The last execution step is incremented PC: typically one if the statement was not a conditional jump, otherwise the increase depends on education and the outcome of this
This elementary cycle can be improved in various ways: for example, the decoding of an instruction can be made simultaneously to the execution of the previous and to the next reading from the memory (instruction prefetch) and the same can be done with the data that is expected It will be needed to the instructions (given prefetch). The same execution of the instructions can be divided into several simple steps, to be performed in successive stages, by organizing the control unit and the ALU in consecutive stages, as the assembly line (pipeline): in this way more instructions can be performed” almost simultaneously “, each occupying at a given instant a different stage of the pipeline.
The problem with this approach are the instructions conditional jump: the CPU cannot know in advance whether or not will have to perform the jump until you’ve completed the previous ones, so it must decide whether to set up pipeline taking into account the jump or not: if of the pipeline goes wrong prediction emptied completely and the instructions being read back from head decoding, losing a number of clock cycles directly proportional to the number of stages of the pipeline. To avoid this modern processors have indoor units ( “Branch prediction unit”) whose purpose is groped to predict whether, given a conditional branch instruction and those performed previously, the jump will be executed or not.
In addition, the processors can implement within them more execution units to perform multiple tasks simultaneously. This approach increases the CPU performance but greatly complicates the execution, given that in order to efficiently perform most operations in parallel, the CPU must be able to organize instruction differently from how they are organized by the programmer ( out of order execution ). A further evolution of this concept has been implemented in multicore processors Itanium, that implement the predicative statements that may or may not be performed depending on the result of other, previously made or simultaneously.
The operating temperature of the CPU varies widely from model to model, generally those for portable devices have a greater operating range and similarly reduced power consumption compared to models intended for fixed locations.
Temperatures can be controlled in various ways, in some models it is not necessary to cool and still is not practicable so congenial because of the characteristics of the machines that must accommodate or not for the fact that it requires as the background to the processor 486 ( also this latter can funionare without a heat sink, but at frequencies below 33 MHz) which models and upcoming need of a passive heat sink, while the processors Pentiumyou also need a fan in order to better dissipate the heat produced.
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